VLSI design
MOS transistors, standard cells, RTL to layout, timing closure
Also known as: Integrated Circuit Design
6 lecture recordings, about 10 hours
Lecture recordings
- Прочие каналы — Verilog by Explore VLSI - VLSI Design & Verification, 31 lectures
- NPTEL — VLSI Design Flow: RTL to GDS, 19 lectures
- Dr Abdul Mannan — VLSI Design (2K19 EE), 64 lectures
- Microelectronics — Integrated Circuit Design and Research, 24 lectures
- Engineering Funda — Complete VLSI Design Flow, 11 lectures
- Engineering Funda — Introduction to VLSI Design, 11 lectures
What you need first
Field of knowledge
The map of knowledge